Optoelectronic devices are well known and it is also known that for such devices it is desirable to minimise the occurrence of defects in the semiconductor layers that form part of the structure of the device. Common defects in LEDs, for example, include threading (edge or screw type) dislocations which can lead to a reduced luminescent efficiency in the final product. The efficiency reduction can, at least in part, arise due to non-radiative recombination that can occur at dislocations and defects. These defects reduce the internal quantum efficiency (IQE) of the device.
One cause of such dislocations, as discussed in WO2006/014472, is lattice mismatches between dissimilar layers. This can arise simply due to different lattice parameters and/or due to thermal contraction at different rates following growth at elevated temperatures. A known technique to address the issue of dislocations arising from different lattice parameters and different rates of thermal contraction is to grow compositionally graded layers between two mismatched layers. Thus, the compositionally graded layer can more closely match the lattice parameters required on each interfacing surface. US2010/0032650 discloses such an intervening layer.
Another known technique to reduce the dislocation density is to deposit a discontinuous passivation interlayer of a material, such as SiNx, and then an island growth layer of GaN or InGaN on the SiNx interlayer to bend the dislocations, followed by a second layer of GaN as disclosed in US2002/0069817. This method usually requires the growth of a thick second layer of GaN to obtain a fully-coalesced continuous low-defect layer.
The present inventors had discovered that the thickness of crack-free GaN layers that can be grown on a silicon substrate is limited and a substantial number of threading dislocations is present in such GaN layers. Furthermore, the inventors realised that any attempt to n-type dope the GaN layer or to include a further n-doped GaN layer on a first GaN layer increases the stress in the layers and exacerbates this problem.
A consequence of the mismatched lattice parameters and thermal expansion coefficients, particularly where the difference lies between the substrate and the overlying layers, is that a high degree of curvature is introduced into the wafer by the mismatch in lattice parameters and thermal expansion coefficients between the substrate and the overlying semiconductor layer. Further, if this curvature means that the overlying layer is in tension then cracks can form in this layer. This curvature also means that large diameter wafers cannot be used in high-volume fabrication facilities and so reduces the size of wafer that can be manufactured cost-effectively or leads to wafers with high defect levels.
Several methods have been proposed to address the issue of tensile stress and associated curvature and/or cracking. Methods include the use of patterned substrates to guide the cracks in masked or etched parts of substrates, the use of compliant substrates or the use of AlGaN layers or the insertion of low-temperature AlN interlayers. To make, for example, GaN-based LEDs on Si substrates by a low-cost route, extra procedures such as ex-situ patterning before growth are not preferred, and a method is required that gives simultaneously crack-free layers, a low threading dislocation density and a flat wafer.
GB2485418 describes a wafer structure that seeks to address at least some of the problems associated with the above-mentioned prior art. The semiconductor material disclosed therein uses a combination of AlGaN layers, GaN layers and SiNx interlayers to provide a high quality material on a silicon substrate for the construction of optoelectronic devices. The wafer is simultaneously flat, crack-free and has an acceptably low dislocation density through careful engineering of the stress in the wafer and control of the threading dislocations. The cost of fabricating the wafer is less than when fabricating a wafer using ex-situ patterning, giving rise to significant commercial advantage.
A key element of the wafer disclosed in GB2485418 was the growth of 3-D islands of GaN through the SiNx interlayers. These islands reduced the propagation of undesirable threading dislocations from the initial nucleation layer into the active regions of the device grown on top of GaN layers grown on top of the 3-D islands. The same inventors subsequently showed that it is possible to grow 3-D islands of GaN directly on the AlN nucleation layer, as described in a published scientific publication (Physics Status Solidi B 247 1752 (2010)). However, it was found that the subsequent growth of AlGaN stress relieving layers introduced additional dislocations that the 3-D island layer was intended to reduce, because the large lattice mismatch between the AlGaN and the GaN. A high aluminium concentration for this AlGaN layer was required in order to provide compositional grading between the AlN nucleation layer and the GaN layers grown above this AlGaN layer. Therefore this particular method disclosed in the above scientific publication is not suitable for the growth of high-quality GaN layers on silicon substrates.
US2005/0037526 discloses a method for the production of a nitride semiconductor wafer. The method relies on the growth of a regular one dimensional array, rather than the growth of isolated crystalline islands.
JP2005235909 discloses a structure intended for short wavelength applications with an active region comprised of GaN and AlGaN. As in US2005/0037526, the structure is grown by external lithographic processing.
US2009/315067 describes a method of reducing the dislocation density without the need for removing the wafer from the growth system as described in the above two applications. The technique described relies on very high levels of doping.